1. Field of the Invention
The present invention relates to a nonvolatile memory and, more particularly, to a single-poly nonvolatile memory cell structure having an erase device on a silicon-on-insulator (SOI) substrate.
2. Description of the Prior Art
Single-poly non-volatile memory is known in the art. FIG. 1 is a schematic layout diagram of a single-poly non-volatile memory cell. As shown in FIG. 1, the single-poly non-volatile memory cell 10 comprises two serially connected PMOS transistors 12 and 14. The PMOS transistor 12 includes a select gate 22, a P+ source doping region 32 and a P+ drain/source doping region 34. The PMOS transistor 14 includes a floating gate 24, the P+ drain/source doping region 34 and a P+ drain doping region 36. The two serially connected PMOS transistors 12 and 14 share the P+ drain/source doping region 34. The single-poly non-volatile memory cell 10 is fully compatible with CMOS logic processes.
In operation, the select gate 22 of the PMOS transistor 12 is coupled to a select gate voltage VSG, the P+ source doping region 32 of the PMOS transistor 12 is electrically coupled to a source line voltage VSL by way of a source line contact, the P+ drain/source doping region 34 and the floating gate 24 are electrically floating, and the P+ drain doping region 36 of the PMOS transistor 14 is electrically coupled to a bit line voltage VBL through a bit line contact. Under the program mode, electrons are selectively injected and stored in the floating gate 24. The memory structure is operated at low voltages.
Because the single-poly non-volatile memory is compatible with standard CMOS logic processes, it is usually applied in the field of embedded memory, embedded non-volatile memory in the mixed-mode circuits and micro-controllers (such as System on Chip, SOC).
There is a trend to make smaller and smaller NVM devices. As the NVM devices become smaller, it is anticipated that the cost per bit of a memory system will be reduced. However, the scalability of the prior art NVM cell is limited by the rule of implanting I/O ion wells that are implanted into the substrate to a junction depth that is deeper than the depth of the shallow trench isolation (STI) in the memory array region.